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1 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com white electronic designs pcmcia flash memory card fle series august 2000 rev. 4 pcmcia flash memory card 8mb through 64 mb (amd based) architecture overview wedc?s fle series is designed to support up to twenty (see block diagram) 32mb components, providing a wide range of density options. cards are based on the am29f032 (32mb) device for 5v only applications. the device code for the am29f032 is 41h and the manufacturer?s id is 01h. systems should be able to recognize these codes. cards utilizing 32mb components provide densities ranging from 8mb to 64mb in 8mb increments. in support of the pc card (pcmcia) standard for word wide access, devices are paired. therefore, the flash array is structured in 64k word blocks. write, read and block erase operations can be performed as either a word or byte wide operation . by multiplexing a0, ce1# and ce2#, 8-bit hosts can access all data on data lines dq0 - dq7. the fle series cards conform with the pc card standard (formerly pcmcia) and supported jeida, providing electrical and physical compatibility. the pc card form factor offers an industry standard pinout and mechanical outline, allowing density upgrades without system design changes. wedc?s standard cards are shipped with wedc?s silkscreen design. cards are also available with blank housings (no silkscreen). the blank housings are available in both a recessed (for label) and at housing. please contact your wedc sales representative for further information on custom artwork. features ? very high density linear flash card ? supports 5v only systems ? based on amd flash components ? low standby power without entering reset mode ? allows standard access from standby mode ? fast read performance ? 150ns maximum access time ? x8/ x16 data interface ? high performance random writes ? 7 s typical word write time ? automated write and erase algorithms ? amd command set ? 1,000,000 erase cycles per block ? 64k word (128kb) symmetrical block architecture ? pc card standard type i form factor general description wedc?s pcmcia flash memory cards offer the highest density, linear flash solid state storage solutions for code and data storage, high performance disk emulation and execute in place (xip) applications in mobile pc and dedicated (embedded) equipment. packaged in a pcmcia type i housing, each card contains a connector, an array of flash memories packaged in tsop packages and card control logic. the card control logic provides the system interface and controls the internal flash memories. combined with le management software, such as flash translation layer (ftl), wedc flash cards provide removable high-performance disk emulation. the wedc fle series is based on amd flash memories. the fle series offers byte wide and word wide operation, low power modes and card information structure (cis) for easy identi cation of card characteristics. note: standard options include attribute memory. cards without attribute memory are available. cards are also available with or without a hardware write protect switch.
2 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com white electronic designs pcmcia flash memory card fle series august 2000 rev. 4 fle block diagram vcc device (n-2) device 1 csn device 2 cs1 cs0 device pair 0 device pair 1 device 3 device pair (n/2 - 1) rh# data bus q0-q7 i/o buffer m res wh# vcc data bus d8-d15 control vcc data bus d0-d7 device (n-1) 0000h wl# rl# data bus q8-q15 device 0 q0-q7 wh# wl# csn rl# rh# q2 qn at/reg enable cs0 q0 control logic pcmcia interface ctrl attrib. mem cis eeprom 2kb we# oe# ce2# ce1# reg# a0 wp address bus control address bus address buffer array address bus a1-a25 device type manuf id device id am29f032 01 h 41 h
3 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com white electronic designs pcmcia flash memory card fle series august 2000 rev. 4 pinout pin signal name i/o function active 35 gnd ground 36 cd1# o card detect 1 low 37 dq11 i/o data bit 11 38 dq12 i/o data bit 12 39 dq13 i/o data bit 13 40 dq14 i/o data bit 14 41 dq15 i data bit 15 42 ce2# i card enable 2 low 43 vs1 o voltage sense 1 n.c. 44 rfu reserved 45 rfu reserved 46 a17 i address bit 17 47 a18 i address bit 18 48 a19 i address bit 19 49 a20 i address bit 20 50 a21 i address bit 21 51 vcc supply voltage 52 vpp2 prog. voltage n.c. 53 a22 address bit 22 8mb (3) 54 a23 address bit 23 16mb (3) 55 a24 address bit 24 32mb (3) 56 a25 address bit 25 64mb (3) 57 vs2 o voltage sense 2 n.c. 58 rst i card reset high 59 wait# o extended bus cycle low (2) 60 rfu reserved 61 reg# i attrib mem select 62 bvd2 o bat. volt. detect 2 (2) 63 bvd1 o bat. volt. detect 1 (2) 64 dq8 i/o data bit 8 65 dq9 i/o data bit 9 66 dq10 o data bit 10 67 cd2# o card detect 2 low 68 gnd ground pin signal name i/o function active 1 gnd ground 2 dq3 i/o data bit 3 3 dq4 i/o data bit 4 4 dq5 i/o data bit 5 5 dq6 i/o data bit 6 6 dq7 i/o data bit 7 7 ce1# i card enable 1 low 8 a10 i address bit 10 9 oe# i output enable low 10 a11 i address bit 11 11 a9 i address bit 9 12 a8 i address bit 8 13 a13 i address bit 13 14 a14 i address bit 14 15 we# i write enable low 16 rdy/bsy# o ready/busy low 17 vcc supply voltage 18 vpp1 prog. voltage n.c. 19 a16 i address bit 16 20 a15 i address bit 15 21 a12 i address bit 12 22 a7 i address bit 7 23 a6 i address bit 6 24 a5 i address bit 5 25 a4 i address bit 4 26 a3 i address bit 3 27 a2 i address bit 2 28 a1 i address bit 1 29 a0 i address bit 0 30 dq0 i/o data bit 0 31 dq1 i/o data bit 1 32 dq2 i/o data bit 2 33 wp o write potect high 34 gnd ground notes: 1. rdy/bsy is an open drain output, external pull-up resistor is required. 2. wait#, bvd1 and bvd2 are driven high for compatibility. 3. shows density for which speci ed address bit is msb. higher order address bits are no connects (i.e., 16mb a23 is msb a24, a25 are nc).
4 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com white electronic designs pcmcia flash memory card fle series august 2000 rev. 4 package dimensions max. 3.370 2.126 0.039 0.063 0.400 0.130 0.039
5 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com white electronic designs pcmcia flash memory card fle series august 2000 rev. 4 card signal description symbol type name and function a0 - a25 input address inputs: a0 through a25 enable direct addressing of up to 64mb of memory on the card. signal a0 is not used in word access mode. a25 is the most signi cant bit dq0 - dq15 input/output data input/output: dq0 through dq15 constitute the bi-directional databus. dq15 is the msb. ce1#, ce2# input card enable 1 and 2: ce1# enables even byte accesses, ce2# enables odd byte accesses. multiplexing a0, ce1# and ce2# allows 8-bit hosts to access all data on dq0 - dq7. oe# input output enable: active low signal gating read data from the memory card. we# input write enable: active low signal gating write data to the memory card. rdy/bsy# output ready/busy output: indicates status of internally timed erase or program algorithms. a high output indicates that the card is ready to accept accesses. a low output indicates that one or more devices in the memory card are busy with internally timed erase or write activities. cd1#, cd2# output card detect 1 and 2: provide card insertion detection. these signals are connected to ground internally on the memory card. the host socket interface circuitry shall supply 10k-ohm or larger pull-up resistors on these signal pins. wp output write protect: write protect re ects the status of the write protect switch on the memory card. wp set to high = write protected, providing internal hardware write lockout to the flash array. if card does not include optional write protect switch, this signal will be pulled low internally indicating write protect = ?off?. vpp1, vpp2 n.c. program/erase power supply: not connected for 5v only card. vcc card power supply: 5.0v for all internal circuitry. gnd ground: for all internal circuitry. reg# input attribute memory select: provides access to flash memory card registers and card information structure in the attribute memory plane. rst input reset: active high signal for placing card in power-on default state. reset can be used as a power-down signal for the memory array. wait# output wait: this signal is pulled high internally for compatibility. no wait states are generated. bvd1, bvd2 output battery voltage detect: these signals are pulled high to maintain sram card compatibility. vs1, vs2 output voltage sense: noti es the host socket of the card?s vcc requirements. vs1 and vs2 are open to indicate a 5v card has been inserted. rfu reserved for future use n.c. no internal connection to card: pin may be driven or left oating
6 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com white electronic designs pcmcia flash memory card fle series august 2000 rev. 4 symbol parameter notes min max units test conditions i li input leakage current 1 20 av cc = v cc max v in =v cc or v ss i lo output leakage current 1 20 av cc = v cc max v out =v cc or v ss v il input low voltage 1 0 0.8 v v ih input high voltage 1 0.7 v cc v cc +0.5 v v ol output low voltage 1 0.4 v i ol = 3.2ma v oh output high voltage 1 v cc -0.4 v cc vi oh = -2.0ma v lko v cc erase/program lock voltage 1 3.25 v notes: 1. values are the same for byte and word wide modes for all card densities. 2. exceptions: leakage currents on ce1#, ce2#, oe#, reg# and we# will be < 500 a when v in = gnd due to internal pull-up resistors. leakage currents on rst will be <150 a when v in =v cc due to internal pull-down resistor. absolute maximum ratings 2 operating temperature t a (ambient) commercial 0c to +60 c industrial -40c to +85 c** storage temperature commercial 0c to +60 c industrial -40c to +85 c** voltage on any pin relative to v ss -0.5v to v cc +0.5v (1) v cc supply voltage relative to v ss -0.5v to +7.0v notes: 1. during transitions, inputs may undershoot to -2.0v or overshoot to v cc +2.0v for periods less than 20ns. 2. stress greater than those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation at these or any other conditions greater than those indicated in the operational sections of this speci cation is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. dc characteristics (1) sym parameter density (mbytes) notes typ(4) max units test conditions i ccr v cc read current all 40(5) 75 ma v cc = v cc max tcycle = 150ns,cmos levels i ccw v cc program current all 30(6) 40(6) ma i cce v cc erase current all 30(6) 40(6) ma i ccs (cmos) v cc standby current 8mb 2,3 50 200 av cc = v cc max control signals = v cc reset = v ss , cmos levels 64mb 100 400 cmos test conditions: v cc = 5v 5%, v il = v ss 0.2v, v ih = v cc 0.2v notes: 1. all currents are rms values unless otherwise speci ed. i ccr , i ccw and i cce are based on word wide operations. 2. control signals: ce1#, ce2#, oe#, we#, reg#. 3. i ccs is speci ed for lowest density card (8mb for two, 32mb components) this represents a single pair of devices. 4. typical: v cc = 5v, t = +25c. 5. the icc current is typically less then 1ma/mhz per device, with with oe not active. 6. icc active while embedded program or erase algorithm is in progress. value based on one device active.
7 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com white electronic designs pcmcia flash memory card fle series august 2000 rev. 4 ac characteristics read timing parameters 150ns sym (pcmcia) parameter min max unit t rc read cycle time 150 ns t a (a) address access time 150 ns t a (ce) card enable access time 150 ns t a (oe) output enable access time 75 ns t su (a) address setup time 20 ns t su (ce) card enable setup time 0 ns t h (a) address hold time 20 ns t h (ce) card enable hold time 20 ns t v (a) output hold from address change 0 ns t dis (ce) output disable time from ce# 75 ns t dis (oe) output disable time from oe# 75 ns t en (ce) output enable time from ce# 5 ns t en (ce) output enable time from oe# 5 ns note: ac timing diagrams and characteristics are guaranteed to meet or exceed pcmcia 2.1 speci cations. read timing diagram note: signal may be high or low in this area. note 1 note 1 a [25::0], reg# ce1#, ce2# oe# d[15::0] tc(r) ta(a) th(a) tv(a) ta(ce) tsu(ce) th(ce) ten(oe) ta(oe) tsu(a) data valid tdis(ce) tdis(oe)
8 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com white electronic designs pcmcia flash memory card fle series august 2000 rev. 4 ac characteristics write timing parameters 150ns sym (pcmcia) parameter min max unit t cw write cycle time 150 ns tw(we) write pulse width 80 ns tsu(a) address setup time 20 ns tsu(a-weh) address setup time for we# 100 ns tsu(ce-weh) card enable setup time for we# 100 ns tsu(d-weh) data setup time for we# 50 ns th(d) data hold time 20 ns trec(we) write recover time 20 ns tdis(we) output disable time from we# 75 ns tdis(oe) output disable time from oe# 75 ns ten(we) output enable time from we# 5 ns ten(oe) output enable time from oe# 5 ns tsu(oe-we) output enable setup from we# 10 ns th(oe-we) output enable hold from we# 10 ns tsu(ce) card enable setup time from oe# 0 ns th(ce) card enable hold time 20 ns note: ac timing diagrams and characteristics are guaranteed to meet or exceed pcmcia 2.1 speci cations. write timing diagram note: 1. signal may be high or low in this area. 2. when the data i/o pins are in the output state, no signals shall be applied to the data pins (d15 -d0) by the host system. th(oe-we) note 1 ce1#, ce2# note 1 tsu(ce-weh) tc(w) a [25::0], reg# tw(we) tdis(we) th(d) d[15::0](din) data input tsu(a) tsu(a-weh) oe# tsu(ce) tsu(d-weh) trec(we) th(ce) tsu(oe-we) tdis(oe) d[15::0](dout) ten(oe) ten(we) note 2 note 2 we#
9 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com white electronic designs pcmcia flash memory card fle series august 2000 rev. 4 data write and erase performance (1, 3) v cc = 5v 5%, 0c t a 60c sym parameter notes min typ(1) max units test conditions t whqv1 t ehqv1 word/byte program time 2,4 7 300 s excludes system-level overhead t whqv2 t ehqv2 block program time 2 0.5 2.0 sec block erase time 2 1 8 sec excludes 00h prog. prior to erasure notes: 1. typical: nominal voltages and t a = 25c. 2. excludes system overhead. 3. valid for all speed options. 4. to maximize system performance, rdy/bsy# signal or component status register should be polled.
10 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com white electronic designs pcmcia flash memory card fle series august 2000 rev. 4 wed 7p016fle2200c15 c995 9915 product marking note: some products are currently marked with our pre-merger company name/ acronym (edi). during our transition period, some products will also be marked with our new company name/acronym (wed). starting october 2001 all pcmcia products will be marked only with the wed pre x. date code lot code / trace number part number company name edi product numbering card access time 15 150ns 25 250ns temperature range c commercial 0c to +70c i industrial -40c to +85c packaging option 00 standard, type 1 card family and version ? see card family and version info. for details (next page) card capacity 016 16mb pc card p standard pcmcia r ruggedized pcmcia card technology 7 flash 8 sram 7 p 016 fle22 00 c 20
11 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com white electronic designs pcmcia flash memory card fle series august 2000 rev. 4 edi7p xxx fle 22 ss t zz based on am29f032 for 5v only applications where xxx: 008 8mb 016 16mb 024 24mb 032 32mb 040 40mb 048 48mb 056 56mb 064 64mb ss: 00 wedc silkscreen 01 blank housing, type i 02 blank housing, type i recessed t: c commercial i industrial zz: 15 150ns note: options without attribute memory and with hardware write protect switch are available. card families: fle 21 - no attribute memory, no wp switch fle 22 - with attribute memory, no wp switch fle 23 - no attribute memory, with wp switch fle 24 - with attribute memory, with wp switch ordering information
12 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com white electronic designs pcmcia flash memory card fle series august 2000 rev. 4 address value description 00h 01h cistpl_device 02h 03h tpl_link 04h 53h writable) 06h 1eh card size: 8mb 3eh 16mb 5eh 24mb 7eh 32mb 9eh 40mb beh 48mb deh 56mb feh 64mb 08h ffh end of device 0ah 18h cistpl_jedec_c 0ch 02h tpl_link 0eh 01h amd - id 10h 41h 29f032 - id 12h 17h cistpl_device_a 14h 03h tpl_link 16h 42h eeprom - 200ns 18h 01h device size = 2kbytes 1ah ffh end of tuple 1ch 1eh cistpl_devicegeo 1eh 06h tpl_link 20h 02h dgtpl_bus 22h 11h dgtpl_ebs 24h 01h dgtpl_rbs 26h 01h dgtpl_wbs 28h 01h dgtpl_part 2ah 01h flash device non-interleaved 2ch 20h cistpl_manfid 2eh 04h tpl_link(04h) 30h f6h editplmid_manf: lsb 32h 01h edi plmid_manf: msb 34h 00h lsb: number not assign. 36h 00h msb: number not assign. 38h 15h cistpl_vers1 3ah 47h tpl_link 3ch 04h tpllv1_major 3eh 01h tpllv1_minor address value description 40h 45h e 42h 44h d 44h 49h i 46h 37h 7 48h 50h p 4ah 30h 0 4ch 1) x 4eh 1) x 50h 46h f 52h 4ch l 54h 45h e 56h 32h 2 58h 2) x 5ah 2dh - 5ch 2dh - 5eh 2dh - 60h 31h 1 62h 35h 5 64h 20h space 66h 00h end text 68h 43h c 6ah 4fh o 6ch 50h p 6eh 59h y 70h 52h r 72h 49h i 74h 47h g 76h 48h h 78h 54h t 7ah 20h space 7ch 45h e 7eh 4ch l 80h 45e e 82h 43h c 84h 54h t 86h 52h r 88h 4fh o 8ah 4eh n 8ch 49h i 8eh 43h c 90h 20h space 92h 44h d address value description 94h 45h e 96h 53h s 98h 49h i 9ah 47h g 9ch 4eh n 9eh 53h s a0h 20h space a2h 49h i a4h 4eh n a6h 43h c a8h 4fh o aah 52h r ach 50h p aeh 4fh o b0h 52h r b2h 41h a b4h 54h t b6h 45h e b8h 44h d bah 20h space bch 00h end text beh 31h 1 c0h 39h 9 c2h 39h 9 c4h 39h 9 c6h 00h end text c8h 00h end of list cis information for fle series cards cis for fle22, 150ns 1) address value description 4ch 30 0 31 1 32 2 33 3 34 4 36 6 4eh 30 0 32 2 34 4 36 6 38 8 2) 58h 32 2 34 4
13 white electronic designs corporation ? (602) 437-1520 ? www.whiteedc.com white electronic designs pcmcia flash memory card fle series august 2000 rev. 4 document title pcmcia flash memory card ? fle series 8mb through 64 mb (amd based) revision history rev # history release date status rev 1 initial release 2-7-98 rev 2 logo change 5-27-99 rev 3 added page 9, heading change on all pages 5-31-00 rev 4 corrected timing errors, pages 6 and 7 8-1-00

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